PIC18F4620-I/ML【PDF 178/286 页】IC MCU FLASH 32KX16 44QFN

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Sheet目录3818

174页 175页 176页 177页 [178页]179页 180页 181页 182页

2008 Microchip Technology Inc.

DS39626E-page 27

PIC18F2525/2620/4525/4620

2.6.5.1

Compensating with the EUSART

An adjustment may be required when the EUSART

begins to generate framing errors or receives data with

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high; to

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low; to

compensate, increment OSCTUNE to increase the

clock frequency.

2.6.5.2

Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is greater than expected, then the internal oscillator

block is running too fast. To adjust for this, decrement

the OSCTUNE register.

2.6.5.3

Compensating with the CCP Module

in Capture Mode

A CCP module can use free-running Timer1 (or

Timer3), clocked by the internal oscillator block and an

external event with a known period (i.e., AC power

frequency). The time of the first event is captured in the

CCPRxH:CCPRxL registers and is recorded for use

later. When the second event causes a capture, the

time of the first event is subtracted from the time of the

second event. Since the period of the external event is

known, the time difference between events can be

calculated.

If the measured time is much greater than the

calculated time, the internal oscillator block is running

too fast; to compensate, decrement the OSCTUNE

calculated time, the internal oscillator block is running

too slow; to compensate, increment the OSCTUNE

REGISTER 2-1:

OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0

R/W-0(1)

U-0

R/W-0

INTSRC

PLLEN(1)

—

TUN4

TUN3

TUN2

TUN1

TUN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

INTSRC: Internal Oscillator Low-Frequency Source Select bit

= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)

= 31 kHz device clock derived directly from INTRC internal oscillator

bit 6

PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)

= PLL enabled for INTOSC (4 MHz and 8 MHz only)

= PLL disabled

bit 5

Unimplemented: Read as ‘0’

bit 4-0

TUN4:TUN0: Frequency Tuning bits

011111

= Maximum frequency

000001

000000

= Center frequency. Oscillator module is running at the calibrated frequency.

111111

100000

= Minimum frequency

Note 1:

Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See

Section 2.6.4 “PLL in INTOSC Modes” for details.

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